A Multi-Chaotic Enhanced Human Evolutionary Optimization Algorithm with FPGA Acceleration for High-Performance Global Optimization

Abstract

Metaheuristic optimization algorithms frequently suffer from premature convergence towards local optima due to inadequate exploration diversity and fixed search strategies. This paper presents MC-HEOA (Multi-Chaotic Enhanced Human Evolutionary Optimization Algorithm), which combines three contributions: (1) the integration of four complementary chaotic maps (Logistic, Tent, Sine, Henon) selected according to dimensional diversity, ergodic properties, and differentiated mixing speeds; (2) a dynamic voting system that selects the operative chaotic map at runtime from the fitness observed at the current iteration, rather than from a choice fixed in advance; and (3) an FPGA implementation of the resulting algorithm on an Artix-7 XC7A100T device. Unlike existing static chaotic integration methods that rely on a predefined map, the proposed mechanism defers the choice of chaotic dynamics to execution, without manual configuration or problem-specific tuning. Experimental validation covers twelve classical benchmark functions, the CEC2022 suite in ten dimensions, and two structural engineering problems (Welded Beam Design and Tension/Compression Spring). The results show that the map which prevails depends on the problem considered: the Logistic map is retained in more than 89% of iterations on the engineering problems, whereas the Henon variant obtains the best average rank on CEC2022, which supports runtime selection over a fixed choice. Against seven recent metaheuristics on CEC2022, the proposed variants outperform WOA, COA and C-KOA across the twelve functions and lead on the hybrid functions F6 and F11, while remaining behind TT-BWKO in overall rank; a Friedman test confirms the significance of the observed ordering ($p = 3.45 \times 10^{-10}$). On the Welded Beam problem, MC-HEOA reaches a cost of 1.6742, improving on the best previously reported result by 2.97%, while on the Tension/Compression Spring problem it is competitive without establishing a new best. The hardware implementation operates at 200~MHz within 2.3~W and occupies 79.6% of the available logic, which positions the algorithm for time-critical optimization in energy-constrained embedded settings.